Title :
Analysis of the extra delay on interconnects caused by resistive opens and shorts
Author :
Maqueda, Pablo ; Rius, Josep
Author_Institution :
Dept. Eng. Electron., Univ. Politec. de Catalunya, Barcelona, Spain
Abstract :
The paper presents an analytical solution for the delay introduced by opens and shorts on RC interconnects. Starting from the set of PDEs that defines the dynamics of such lines, complete solutions are found. Compact expressions for the delay, derived from the complete solutions, show an excellent agreement when compared with simulations, for realistic values of interconnect parameters, driver resistance and an arbitrary values and place of the defect. This information is useful for testing of such interconnects.
Keywords :
delays; digital integrated circuits; integrated circuit interconnections; integrated circuit testing; RC interconnects; digital IC interconnects; driver resistance; extra delay analysis; resistive opens; resistive shorts; Decision support systems; Delay;
Conference_Titel :
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location :
Sesimbra, Lisbon
Print_ISBN :
978-1-4244-4596-7
Electronic_ISBN :
978-1-4244-4595-0
DOI :
10.1109/IOLTS.2009.5196016
