Using FPGAs to Supplement Ray-Tracing Computations on the Cray XD-1

Optical ray tracing simulations in lens design commonly employ six major computations: the point of intersection of a ray and an optical surface, a check to see whether the ray is inside a restrictive aperture, calculation of a unit vector normal to the surface at the point of intersection, the result of reflection or refraction of the ray at the surface, and coordinate conversions of the new ray´s starting position and direction to facilitate repetition of the calculations at succeeding optical elements. Because the rays are independent of one another, ray tracing can benefit greatly from parallel processing, especially when there are billions of rays to be traced. The efficiency of using 839 AMD Opteron processors for this application has been shown to be 97.9 %. This means that adding additional processors is a highly effective strategy for increasing the rate of ray tracing, thus reducing the time of simulation. Using field-programmable gate arrays (FPGA) is an effective strategy for further increasing the rate of ray tracing. In this paper we describe key aspects of implementing deeply pipelined processors within an FPGA to perform scientific computations, using them to supplement the ray tracing provided by the sequential Opteron processors in the Cray XD-1. The discussion includes how to schedule the use of the FPGA´s internal resources, synchronize the interaction between the FPGA and the Opterons, and assess the fraction of time that each major computational resource within the FPGA is in use. We discuss a method that guarantees 100 % efficiency of the critical resource, the resource needed most often for a specific computation. We also consider how to increase the efficiency of the non-critical computational resources within the FPGA and what the side effects of such changes can be.