CMOS design of pulse coded adaptive neural processing element using neural-type cells

The authors present the CMOS design of an adaptive neural processing element (NPE). The CMOS circuit encodes information using pulse coded neural-type cells (NTC). The synaptic junctions are realized by voltage-controlled resistors in the NTC where the conductance of these resistors determine weights. The information is coded into a form of pulse duty cycle. The pulse duty cycle modulation (PDCM) technique is briefly reviewed. Weights, expressed in terms of the pulse duty cycle, are adaptively controlled through feedback circuits using a simple differential amplifier. This differential amplifier compares the present output with a desired reference value. The difference is used to adjust the weights through changing of the equivalent resistance value of the voltage-controlled resistor in the NTC. Simulation results of simple examples verified the design concepts