Competitive learning in asynchronous pulse density integrated circuits

The authors introduce a MOS circuit for the integrated implementation of pulse-coded competitive learning. They describe an autoadaptive synapse circuit for a pulse-coded competitive learning rule. The specific focus is upon an adaptive synapse cell which combines a capacitive analog storage element with subthreshold adaptation circuitry. The adaptation circuitry is designed to compensate for nonlinear device transconductance in the subthreshold operating region. The simulation results presented verify circuit operation in a 2-input-3-output competitive network. Accurate clustering of random training data was demonstrated