Title :
Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
Author :
O´Brien, P.R. ; Savarino, T.L.
Author_Institution :
Digital Equipment Corp., Marlborough, MA, USA
Abstract :
An efficient algorithm is presented which accounts for series resistance by computing a reduced-order approximation for the driving-point admittance of an RC tree. The algorithm consists of four rules which allow the Taylor series expansion coefficients of the driving-point admittance looking downstream of a given point in the tree to be correctly propagated further upstream. Rules 1-3 involve movement upstream, along a single branch, and past, respectively, a lumped capacitor to ground, a series lumped resistor, and a uniformly distributed RC segment. Rule 4 involves combining two or more different admittance expansions in parallel at a branch point in the tree. Using an emitter-coupled-logic clock buffer as an example, the authors demonstrate a significant improvement in accuracy.<>
Keywords :
clocks; delays; emitter-coupled logic; integrated circuit technology; RC tree; Taylor series expansion coefficients; accurate delay estimation; driving-point admittance; driving-point characteristic; emitter-coupled-logic clock buffer; lumped capacitor to ground; reduced-order approximation; resistive interconnect; series lumped resistor; series resistance; uniformly distributed RC segment; Admittance; Capacitance; Clocks; Delay effects; Delay estimation; Integrated circuit interconnections; Propagation delay; System performance; System-on-a-chip; Voltage;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.77002
