A bit-level systolic array for delayed LMS adaptive FIR filtering

Author

Wang, Chin-Liang ; Tsou, Hseng-Ching

Author_Institution

Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

5

fYear

1992

fDate

10-13 May 1992

Firstpage

2136

Abstract

A bit-serial bit-level systolic array based on a new scheme for multiplication and inner product computation is presented to implement delayed least-mean-square (DLMS) adaptive N-tap finite-impulse-response (FIR) filters. The architecture has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N /2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance with proper selection of the step size

Keywords

adaptive filters; delays; digital filters; least squares approximations; systolic arrays; bit-level systolic array; delayed LMS adaptive FIR filtering; filter coefficient adaptation; inner product computation; multiplication; throughput rate; Adaptive filters; Computer architecture; Delay; Filtering; Finite impulse response filter; Least squares approximation; Signal processing algorithms; Systolic arrays; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230570

Filename

230570