A novel current model for CMOS gates

Author

Wang, Jyh Herng ; Fan, Jeng Ten ; Feng, Wu Shiung

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

5

fYear

1992

fDate

10-13 May 1992

Firstpage

2132

Abstract

The current waveform of a CMOS gate can be divided into three regions and the characteristics in each region can be approximated by an exponential function. After analyzing the possible transition of a gate, the current waveform under one input vector can be obtained with only four parameters. The work is based on a switch-level timing simulation for various input vectors. The simulated current waveform, instead of the average estimation, helps in solving VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE and the model, agreement was obtained, especially for the time points where current pulses occur

Keywords

CMOS integrated circuits; adders; circuit reliability; integrated logic circuits; logic gates; CMOS gates; VLSI reliability; current model; current pulses; current waveform; electromigration; excess voltage drops; exponential function; full adder; power buses; switch-level timing simulation; Capacitance; Circuit synthesis; Electromigration; Failure analysis; Integrated circuit modeling; Integrated circuit reliability; Semiconductor device modeling; Timing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230571

Filename

230571