High-k dielectric polycrystallization effects on the nanoscale electrical properties of MOS structures

High-k dielectrics have been introduced in MOS devices to reduce gate leakage currents. However, their polycrystallization during a thermal annealing can affect the electrical properties and reliability of scaled devices. In this work, a Conductive Atomic Force Microscope (CAFM) has been combined with standard electrical characterization techniques at wafer level to investigate (I.) how the polycrystallization of a high-k layer affects its nanoscale morphological and electrical properties and (II.) how such nanoscale properties affect the electrical characteristics of fully processed devices. The impact of an electrical stress on the electrical conduction and charge trapping of amorphous and polycrystalline high-k layers has been also analyzed.