Author_Institution :
National Semiconductor Corp., Santa Clara, CA, USA
Abstract :
The architecture of PACE (Processing and Control Element) microprocessor, organized to minimize external components, and provide a powerful instruction set, will be discussed. A parallel 16-bit, single-chip CPU, implemented in P-channel, silicon-gate technology. It features four general-purpose accumulators, a 10-word stack, interrupt logic, control and status flags, a 16-bit ALU, requires single-phase, true and complement clocks, and a typical execution time of 10μs.
