• DocumentCode
    2858426
  • Title

    Flip chip micropallet technology-a chip-scale chip

  • Author

    Goetz, Martin

  • Author_Institution
    Alpine Microsyst., Campbell, CA, USA
  • fYear
    1998
  • fDate
    15-17 Apr 1998
  • Firstpage
    526
  • Lastpage
    530
  • Abstract
    The complex IC is a novel semiconductor construct, combining trailing edge ICs with leading edge ICs to solve integration problems. Using this approach gives the IC systems designer greater flexibility in working in the world of high speed and mixed technology. Cost and manufacturing problems associated with other approaches, such as system-on-a-chip (SOC) and multichip modules (MCM) limit their market availability and affordability. Part of the cost is related to flipping the die on to a substrate, carrier or package. Besides the common issues related to CTE mismatches of materials, requiring underfill as a process, there is also the cost of designing and processing a redistribution layer on the IC. This paper discusses the manufacturing and technical attributes of using micropallet technology and flip chip wafer level processing to accomplish reliable known good die (KGD) capability for complex IC integration. The paper emphasizes the necessities required to achieve reliable fine-pitch bumping and chip placement, and also highlights some potential applications which can benefit from micropallet technology
  • Keywords
    fine-pitch technology; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit yield; microassembling; CTE mismatch; IC integration; IC redistribution layer; IC systems design flexibility; affordability; chip placement; chip-scale packaging; complex IC; complex IC construct; complex IC integration; die carrier; die package; flip chip micropallet technology; flip chip wafer level processing; high speed mixed technology; market availability; micropallet technology; multichip modules; package cost; package manufacturing; reliable fine-pitch bumping; reliable known good die capability; system-on-a-chip; underfill process; Costs; Flip chip; High speed integrated circuits; Lead compounds; Multichip modules; Packaging; Semiconductor device manufacture; Substrates; System-on-a-chip; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multichip Modules and High Density Packaging, 1998. Proceedings. 1998 International Conference on
  • Conference_Location
    Denver, CO
  • Print_ISBN
    0-7803-4850-8
  • Type

    conf

  • DOI
    10.1109/ICMCM.1998.670836
  • Filename
    670836