Designing a testable system on a chip

Author

Kosonocky, Stephen V. ; Bright, Arthur ; Warren, Kevin ; Haring, Ruud A. ; Klepner, Steve ; Asaad, Sameh ; Basavaiah, S. ; Havreluk, Bob ; Heidel, Dave ; Immediato, Michael ; Jenkin, K. ; Joshi, Rajiv ; Parker, Ben ; Rajeevakumar, T.V. ; Stawiasz, Kevin

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1998

fDate

26-30 Apr 1998

Firstpage

2

Lastpage

7

Abstract

A “system on a chip” is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described

Keywords

CMOS integrated circuits; VLSI; built-in self test; design for testability; mixed analogue-digital integrated circuits; production testing; 0.5 micron; 16 Mbit; ASIC; CMOS; DRAM macro isolation; built-in self test; design for testability; externally accessible analog circuitry; functional debugging; level-sensitive scan design logic; logic tester; low cost manufacturing test; system on a chip; Application specific integrated circuits; Automatic testing; CMOS logic circuits; CMOS process; Circuit testing; Digital-analog conversion; Integrated circuit testing; Logic testing; Random access memory; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670841

Filename

670841