• DocumentCode
    2858633
  • Title

    A new path tracing algorithm with dynamic circuit extraction for sequential circuit fault diagnosis

  • Author

    Shigeta, K. ; Ishiyama, T.

  • Author_Institution
    Device Analysis & Evaluation Technol. Center, NEC Corp., Kawasaki, Japan
  • fYear
    1998
  • fDate
    26-30 Apr 1998
  • Firstpage
    48
  • Lastpage
    53
  • Abstract
    The authors propose a new diagnosis technique based on path tracing, which diagnoses fault locations in a sequential circuit by extracting combinational circuit blocks dynamically and tracing error propagation paths from failed primary outputs to fault origins. The dynamic circuit extraction reduces analysis area, which is suitable for a large circuit. By applying this technique to several ISCAS´89 benchmark circuits, the authors demonstrated that this technique could localize faults into 20 candidates within four hours
  • Keywords
    automatic testing; fault location; logic testing; performance evaluation; sequential circuits; ISCAS´89 benchmark circuits; combinational circuit blocks; dynamic circuit extraction; error propagation paths; failed primary outputs; fault locations; fault origins; inverse logic inference; path tracing algorithm; sequential circuit fault diagnosis; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Dictionaries; Failure analysis; Fault diagnosis; Heuristic algorithms; Sequential circuits; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1998. Proceedings. 16th IEEE
  • Conference_Location
    Monterey, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-8436-4
  • Type

    conf

  • DOI
    10.1109/VTEST.1998.670848
  • Filename
    670848