Title :
Performance test case generation for microprocessors
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such rest cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre- and post-silicon stages of development
Keywords :
computer testing; fault location; integrated circuit testing; microprocessor chips; parallel architectures; performance evaluation; pipeline processing; diagnosing; microprocessors; performance bugs; performance test cases; pipeline flow behavior; post-silicon stages; pre-silicon stages; real superscalar processor; timing; Computer aided software engineering; DSL; Gold; Hardware; Microprocessors; Pipelines; Predictive models; Testing; Timing; Visualization;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670849
