The role of the parasitic capacitance of the inductor in boost converters with normally-on SiC JFETs

In this paper the impact of the parasitic capacitance of the inductor on the performance of a fast-switching boost converters with SiC JFETs is discussed. Two inductor designs, one conventional and another with a space between the winding layers, are investigated and their parasitic capacitances are measured by different methods. The air-gap between the winding layers reduced the inductor self-capacitance more than 8 times. The two inductors were used in a 2 kW, 100 kHz boost converter with a normally-on SiC JFET and their performance was compared. When the inductor with a low self-capacitance was used, there were fewer oscillations during the switching transients and the losses were reduced about 16 %.