Title :
Ground bounce considerations in DC parametric test generation using boundary scan
Author :
Majumdar, Amitava ; Komoda, Michio ; Ayres, Tim
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount of ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits
Keywords :
VLSI; automatic testing; boundary scan testing; integrated circuit testing; logic testing; production testing; DC parametric test generation; boundary scan; ground bounce considerations; input DC tests; output DC tests; test time; time constraints; Automatic testing; Circuit noise; Circuit testing; DC generators; Integrated circuit testing; Logic testing; RLC circuits; Switches; Switching circuits; Voltage;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670853