Gating and Serializing the Data Path of CPU for Low Power Consumption

Data path is one of the major power consuming parts of the CPU. Low power high performance processors are the demands of the consumers. The current processors in the market provide enhanced performance, but the factor that we consider is the power consumption. The paper focuses on effective power conserving techniques in the data path including gating the data path and reducing the number of bus lines. Gating the data path can help in reducing the redundant calculations that cause wastage of power in normal processors. We also analyze the power consumption while reducing the number of bus lines in the data path. Our design is based on 32-bit ALU on the data path. We begin with 32-bit parallel inputs for ALU, and then reduce the input bus lines to 16, 8 and so on, until input serialization is achieved. The power variation that is brought about by reducing the input data lines is estimated using Xilinx ISE 10.1. The first section of the paper describes the parameters that are responsible for higher power consumption in bus lines. This is followed by details on gating the data path with the implementation of the ALU and the power estimation for all different configurations of data input lines. The last part of the paper consists of the results of power estimation for varying data input lines and the power comparison for a gated and a non-gated ALU.