New Latch-Up Model for Deep Sub-micron Integrated Circuits

Author

Dong, Pan ; Fan, Long ; Yue, Suge ; Zheng, Hongchao ; Du, Shougang

Author_Institution

Design Dept., Beijing Microelectron. Technol. Inst., Beijing, China

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

31

Lastpage

36

Abstract

This paper mainly simulated the single event latch-up (SEL) for the CMOS inverter under the 0.18um technology. The SEL of integrated circuit (IC) was also analyzed in detail. The result showed that the parasitic lateral transistors NPN and PNP of NMOS and PMOS play a role in the SEL happening process. The changes of the drain voltage and the drain current and the functional failure of the circuit were also explained in further. Therefore the new SEL model could be established.

Keywords

CMOS integrated circuits; MOSFET; flip-flops; invertors; CMOS inverter; NMOS play; NPN; PMOS play; PNP; SEL happening process; deep sub-micron integrated circuits; drain current; drain voltage; functional failure; latch-up model; parasitic lateral transistors; single event latch-up; Anodes; Cathodes; Integrated circuit modeling; MOS devices; Substrates; Transient analysis; Transistors; (SEL); Single event effects (SEE); inverter; large scale integrated circuit (VLSI);

fLanguage

English

Publisher

ieee

Conference_Titel

Dependable, Autonomic and Secure Computing (DASC), 2011 IEEE Ninth International Conference on

Conference_Location

Sydney, NSW

Print_ISBN

978-1-4673-0006-3

Type

conf

DOI

10.1109/DASC.2011.30

Filename

6118349