A Wide-Range Edge-Combining DLL with a Charge Pump for Low Spur

This paper describes a wide-range edge combining DLL which overcomes the range problem and reduces output spur by using a start-control circuit and new charge pump. Theoretically the lock range can be extended to f<; 1 / T_VCDL (min) where T_VCDL (mill) is the minimum value of the voltage-controlled delay line. By employing eight same delay cells, the frequency-multiplied output can be reached up to X2 and X4. Output spur is suppressed by decreasing the non-ideal impact of the charge pump. The proposed DLL frequency synthesizer, which has been realized in a CMOS 0.18um process, consumption about 18 mW. The output spur for X2 achieve 34 dB and the phase noise at 1- MHz frequency offset after X2 is -126.0 dBc/Hz.