Reliability Implications of Register Utilization: An Empirical Study

Physical memory faults are one of the accepted reliability threats for modern processor technology. Even though error correction for memory hardware can deal with this class of fault, many processor designs such as X86 do not invest semiconductor complexity and space to deal with multi-bit faults in caches and registers. In this paper, we analyze how the right choice of compiler options can act as software-based error prevention strategy for register file faults. This investigation is based on a classification scheme for GCC compiler options and a new fault injection environment for automated experiments. The study proves the the initial hypothesis that reliability improvements mainly depend on the algorithmic structure of the application under test. A small number of compiler options have proven to be a feasible application-independent error mitigation strategy.