Title :
A simple and efficient method for generating compact IDDQ test set for bridging faults
Author :
Shinogi, Tsuyoshi ; Hayashi, Terumine
Author_Institution :
Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
Abstract :
This paper presents an efficient method for generating a compact test set for IDDQ testing of bridging faults in combinational CMOS circuits. This method is based on the iterative improvement method. Though our method is simple and easy to implement, it is efficient. Experimental results for large ISCAS benchmark circuits demonstrate its efficiency in comparison with results of previous methods
Keywords :
CMOS logic circuits; automatic testing; combinational circuits; integrated circuit testing; iterative methods; logic testing; IDDQ testing; bridging faults; combinational CMOS circuit; compact IDDQ test set generation; iterative improvement method; Circuit faults; Circuit testing; Compaction; DC generators; Electrical fault detection; Electronic equipment testing; Fault detection; Logic testing; System testing; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670857
