Experimental results for IDDQ and VLV testing

Author

Chang, Jonathan T Y ; Tseng, Chao-Wen ; Chu, Yi-Chin ; Wattal, Sanjay ; Partell, M. ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

1998

fDate

26-30 Apr 1998

Firstpage

118

Lastpage

123

Abstract

An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed the Stage 1 tests were packaged for further investigation. This paper describes the experimental setup and the preliminary results for the final package test. We focus on the correlation among various defect classes, including IDDQ failures, Very-Low-Voltage (VLV) failures, timing-independent combinational (TIC) defects, and non-TIC defects. We used 2 supply voltages for VLV tests. Two test speeds were used at each supply voltage. 9 dies failed only the VLV Boolean tests, and 7 of these were confirmed to have had high IDDQ measurement results. We also investigated the defect classes of the test escapes for 100% single stuck fault (SSF), transition fault, and IDDQ test sets

Keywords

digital integrated circuits; integrated circuit testing; logic testing; timing; IDDQ failures; IDDQ test sets; IDDQ testing; VLV Boolean tests; VLV testing; defect classes; experimental test chip; final package test; single stuck fault; test techniques evaluation; timing-independent combinational defects; transition fault; very-low-voltage failures; wafer probe; Circuit testing; Clocks; Logic arrays; Logic testing; Packaging; Sampling methods; System testing; Timing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670858

Filename

670858