DocumentCode :
2859642
Title :
Efficient path selection for delay testing based on partial path evaluation
Author :
Tani, Seiichiro ; Teramoto, Mitsuo ; Fukazawa, Tomoo ; Matsuhiro, Kazuyoshi
Author_Institution :
NTT Opt. Netwirk Syst. Lab., Japan
fYear :
1998
fDate :
26-30 Apr 1998
Firstpage :
188
Lastpage :
193
Abstract :
In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage
Keywords :
VLSI; delays; digital integrated circuits; integrated circuit testing; logic testing; VLSI circuits; delay testing; fault coverage; partial path evaluation; path selection; Delay; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
ISSN :
1093-0167
Print_ISBN :
0-8186-8436-4
Type :
conf
DOI :
10.1109/VTEST.1998.670867
Filename :
670867
Link To Document :
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