DocumentCode :
2859660
Title :
On delay-untestable paths and stuck-fault redundancy
Author :
Majumder, Subhashis ; Agrawal, Vishwani D. ; Bushnell, Michael L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear :
1998
fDate :
26-30 Apr 1998
Firstpage :
194
Lastpage :
199
Abstract :
We explore non-robust untestability of paths based on redundant stuck-at faults. Such untestability classification is necessary for a path to be ignored in timing verification and delay testing. A recent result states that redundant stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) faults of a line imply untestability of rising and falling delay faults, respectively, for all paths through that line. We find that this result only establishes robust untestability of paths. Starting with known examples, where a non-robust test can exist for some paths that pass through the site of a redundant stuck-at fault, we examine various classes of stuck-at fault redundancies. We prove that: (1) an unexcitable or undrivable redundant s-a-0 (s-a-1) fault will make all paths through the fault site non-robustly delay-untestable for rising (falling) transition, and (2) an unobservable fault site (causing both s-a-0 and s-a-1 faults to be redundant) can only classify the passing paths as robustly delay-untestable, Finally, we show that two singly-untestable paths, passing through the sites of separate redundant single stuck-at faults, may form a multiply-testable pair of paths provided the two redundant single stuck-at faults have a multi-fault test
Keywords :
VLSI; delays; digital integrated circuits; integrated circuit testing; logic testing; redundancy; timing; delay testing; delay-untestable paths; multi-fault test; stuck-at faults; stuck-fault redundancy; timing verification; untestability classification; Circuit faults; Circuit testing; Delay; Design automation; Electronic equipment testing; Logic testing; Redundancy; Sequential analysis; Sequential circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
ISSN :
1093-0167
Print_ISBN :
0-8186-8436-4
Type :
conf
DOI :
10.1109/VTEST.1998.670868
Filename :
670868
Link To Document :
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