Sampling techniques of non-equally probable faults in VLSI systems

Author

Goncalves, F.M. ; Teixeira, J.P.

Author_Institution

IST, INESC, Lisbon, Portugal

fYear

1998

fDate

26-30 Apr 1998

Firstpage

283

Lastpage

288

Abstract

The purpose of this paper is to present a novel methodology for defect-oriented (DO) fault sampling, and its implementation in a new extraction tool, lobs. The methodology is based on the statistics theory, and on the application of the concepts of estimation of totals over subpopulations and stratified sampling to the fault sampling problem. The proposed sampling methodology applies to non-equally probable DO faults, exhibiting a wide range of probabilities of occurrence, and leads to confidence intervals similar to the ones obtained with equally probable faults. ISCAS´85 benchmark circuits are laid out and lobs used to ascertain the results

Keywords

VLSI; estimation theory; fault diagnosis; integrated circuit testing; random processes; statistical analysis; ISCAS´85 benchmark circuits; VLSI systems; confidence intervals; defect-oriented fault sampling; estimation; fault sampling; nonequally probable faults; sampling techniques; statistics theory; stratified sampling; subpopulations; Circuit faults; Fault detection; Probability; Production; Sampling methods; Statistics; Testing; US Department of Transportation; Uncertainty; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670881

Filename

670881