Title :
Design-for-testability for switched-current circuits
Author :
Renovell, M. ; Azaïs, F. ; Bodin, J.C. ; Bertrand, Y.
Author_Institution :
LIRMM, Montpellier, France
Abstract :
In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode
Keywords :
controllability; design for testability; observability; switched current circuits; DFT technique; SI circuits; controllability; design-for-testability; fully testable structure; hardware configuration; observability; switched-current circuits; timing configuration; Analog circuits; Built-in self-test; Circuit faults; Circuit testing; Clocks; Filters; Hardware; Integrated circuit interconnections; Switching circuits; Timing;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670892
