DocumentCode
2860129
Title
A methodology for transforming memory tests for in-system testing of direct mapped cache tags
Author
Al-Harbi, S.M. ; Gupta, Sandeep K.
Author_Institution
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear
1998
fDate
26-30 Apr 1998
Firstpage
394
Lastpage
400
Abstract
While any efficient test developed for off-line testing of memory chips can be easily adapted for in-system testing of single level memory systems, no efficient methodology is known to transform such a test for in-system testing of multilevel memory systems that have one or more levels of cache. The main challenge is in transforming the known test to test the tags of the cache (testing of the data part of the cache is relatively straightforward). In this paper we present a general methodology to transform march tests for in-system testing of tags of direct mapped caches. The transformation has been used to obtain new versions of March B and March X tests. It is shown that the new versions of tests detect the same sets of faults in the cache tags as their original versions detect in memory chips. Finally, it is demonstrated that the proposed version of March B has significantly lower time complexity than previously proposed tests and can be applied without any modification of the memory system hardware
Keywords
cache storage; computational complexity; fault diagnosis; integrated circuit testing; integrated memory circuits; March B test; March X test; bridging faults; cache model; cache tags; coupling faults; direct mapped cache tags; in-system testing; memory tests; multilevel memory; stuck at fault; time complexity; Decoding; Fault detection; Observability; System testing; Technical Activities Guide -TAG;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location
Monterey, CA
ISSN
1093-0167
Print_ISBN
0-8186-8436-4
Type
conf
DOI
10.1109/VTEST.1998.670897
Filename
670897
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