A nonenumerative ATPG for functionally sensitizable path delay faults

Author

Karayiannis, Dimitrois ; Tragoudas, Spryos

Author_Institution

Texas Instrum. Inc., San Jose, TX, USA

fYear

1998

fDate

26-30 Apr 1998

Firstpage

440

Lastpage

445

Abstract

This paper presents a test pattern generator for path delay faults which generates a polynomial number of test patterns that target a large number of functionally sensitizable faults. The number of these faults may be exponential to the input site. Experimental results are presented on the ISCAS´85 benchmarks

Keywords

VLSI; automatic testing; delays; fault diagnosis; integrated circuit testing; logic testing; ISCAS´85 benchmarks; functionally sensitizable path delay faults; input site; nonenumerative ATPG; polynomial number; Automatic test pattern generation; Benchmark testing; Clocks; Fault detection; Instruments; Permission; Polynomials; Propagation delay; Robustness; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670908

Filename

670908

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2860332