Title :
A nonenumerative ATPG for functionally sensitizable path delay faults
Author :
Karayiannis, Dimitrois ; Tragoudas, Spryos
Author_Institution :
Texas Instrum. Inc., San Jose, TX, USA
Abstract :
This paper presents a test pattern generator for path delay faults which generates a polynomial number of test patterns that target a large number of functionally sensitizable faults. The number of these faults may be exponential to the input site. Experimental results are presented on the ISCAS´85 benchmarks
Keywords :
VLSI; automatic testing; delays; fault diagnosis; integrated circuit testing; logic testing; ISCAS´85 benchmarks; functionally sensitizable path delay faults; input site; nonenumerative ATPG; polynomial number; Automatic test pattern generation; Benchmark testing; Clocks; Fault detection; Instruments; Permission; Polynomials; Propagation delay; Robustness; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670908
