DocumentCode :
2860357
Title :
Evaluation of an Esterel-based hardware/software co-design flow
Author :
Roessler, Peter ; Zauner, Martin
Author_Institution :
Univ. of Appl. Sci. Technikum Wien, Vienna, Austria
fYear :
2009
fDate :
8-10 July 2009
Firstpage :
42
Lastpage :
45
Abstract :
This work describes the evaluation of a hardware/software co-design flow based on the synchronous language Esterel. The paper starts with a short introduction into Esterel and tackles available tools. The focus of this work is an examination of the design flow concerning the practical applicability, based on case studies and related work. Advantages and draw-backs of the design flow are discussed and compared to traditional hardware/software design flows.
Keywords :
hardware-software codesign; high level languages; software performance evaluation; Esterel; hardware/software codesign flow; synchronous language; Circuits; Embedded software; Embedded system; Engines; Field programmable gate arrays; Hardware design languages; Instruments; Software design; Software systems; Space exploration; Embedded Systems Design; Esterel; Hardware/Software Co-Design; Synchronous Languages;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Embedded Systems, 2009. SIES '09. IEEE International Symposium on
Conference_Location :
Lausanne
Print_ISBN :
978-1-4244-4109-9
Electronic_ISBN :
978-1-4244-4110-5
Type :
conf
DOI :
10.1109/SIES.2009.5196190
Filename :
5196190
Link To Document :
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