Title :
New techniques for deterministic test pattern generation
Author :
Hamzaoglu, Ilker ; Patel, Janak H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance
Keywords :
VLSI; automatic testing; combinational circuits; integrated circuit testing; logic testing; sequential circuits; ATOM; ATPG system; ISCAS85 benchmark circuits; ISCAS89 benchmark circuits; PODEM algorithm; VLSI circuits; backtracks; combinational circuits; computational cost; deterministic test pattern generation; full scan version; signal line assignments; test generation; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Computational efficiency; Object oriented modeling; Signal generators; System testing; Test pattern generators; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670910
