The design, fabrication and performance of digital poly-Si thin film transistor circuits on glass

The author presents results of some digital CMOS circuits which were fabricated using a low temperature process. All the results presented were obtained on devices and circuits fabricated on glass substrates. The active layer of the transistor was 1500 Å of undoped polysilicon, formed by deposition of a-Si (using a Rytrak LPCVD reactor) onto Hoya NA40 glass substrates, followed by a crystallisation anneal at 600°C. The gate and passivation insulators were SiO₂ , deposited by APCVD. Phosphorus and boron implants were performed after patterning of the poly-Si gate so as to obtain self-aligned NMOS and PMOS TFTs. The TFTs were completed with aluminium metallisation. ITO was used for the pixel electrodes and columns. Plasma hydrogenation was not used. Circuit measurements were carried out on four batches, with average TFT parameters as follows: threshold voltages and mobilities were 11.5 V and 27 cm²/V/s for NMOS and -17.5 V and 29 cm²/V/s for PMOS devices. Transfer characteristics currently obtained on this process when optimised for on-current are shown