DocumentCode
2860766
Title
On link harness optimization of embedded Ethernet networks
Author
Sommer, Jorg ; Doumith, Elias A. ; Duva, Quentin
Author_Institution
Inst. of Commun. Networks & Comput. Eng. (IKR), Univ. of Stuttgart, Stuttgart, Germany
fYear
2009
fDate
8-10 July 2009
Firstpage
191
Lastpage
200
Abstract
During the last decades, Ethernet progressively became the most widely used local area network (LAN) technology. It evolved from a bus topology to a micro-segmented network with full duplex links. Apart from LAN installations, Ethernet became also attractive for embedded application areas such as industrial, automotive, and avionics. In these areas, the connectivity between the nodes and the switches results in link harnesses. These harnesses can be bundled together and installed inside ducts. Since not all the links have the same endpoints, some full duplex links leave a duct at points referred to as junction points. In this paper, we propose a simulated annealing based algorithm to optimize the topology design of embedded Ethernet networks. This algorithm finds the (near-)optimal positions of a given number of switches and their connections to given nodes. When we take into account that links are organized into link harnesses and installed into ducts, we have to find also the number of junction points required as well as their optimal positions. For this purpose, we propose two algorithms. Finally, we compare the algorithms in terms of computation time and the quality of the obtained solution, and we highlight the cost benefits of bundling links and installing them into ducts.
Keywords
local area networks; simulated annealing; telecommunication network topology; LAN technology; bus topology; embedded Ethernet network; full duplex link; link harness optimization; local area network technology; microsegmented network; simulated annealing based algorithm; topology design; Aerospace electronics; Algorithm design and analysis; Automotive engineering; Design optimization; Ducts; Ethernet networks; Local area networks; Network topology; Simulated annealing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Embedded Systems, 2009. SIES '09. IEEE International Symposium on
Conference_Location
Lausanne
Print_ISBN
978-1-4244-4109-9
Electronic_ISBN
978-1-4244-4110-5
Type
conf
DOI
10.1109/SIES.2009.5196215
Filename
5196215
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