A study of partitioned vector register files

The authors study partitioned video register files, where multiple vector registers are connected by a pair of buses to a set of functional units. Although less costly to implement, this alternative organization places some restrictions on accessing vector registers, thus potentially degrading processor performance. To circumvent this restrictive access, the authors develop a heuristic algorithm for assigning vector registers in a partitioned vector register file. By compiling a set of benchmarks with the proposed assignment algorithm, the authors generated data showing that the performance of this alternative register organization is comparable to that of a traditional one. Moreover, the data show that eight pairs of buses are adequate for a Cray Y-MP vector processor. If each pair of buses services two vector registers, for a total of 16, the algorithm successfully assigns 94% of the benchmark loops. Using 32 vector registers raises this percentage to 97%