Improvement of nano MOSFET ultra thin gate leakage and driving current with low temperature polygen process

Effect of poly Si deposition temperature on gate leakage and reliability are investigated in details. We reduce the poly Si grain size by lowering deposition temperature. A small grain size can provide smoother interface to an ultra-thin gate oxide than a big one, thus achieving low sub-threshold leakage and gate leakage. Besides, the driving currents are respectively increased ~5% and ~3% for n- and p- MOSFETs, as the temperatures are lowered from 715 to 705°C. The most importance is that the small grain size does not degrade the gate oxide integrity and device junction leakage current.