Design using VHDL for synthesis and test

Synthesis can be achieved from the majority of VHDL but some constructs are restricted. The techniques used in the TransGATE system to synthesise VHDL are explained here. The ideas will be useful for those who wish to understand the process of designing hardware from VHDL models. The main consideration for users of synthesis is to develop the design using a synchronous design methodology since there will be reduced test coverage for asynchronous circuits. With this restriction, synthesis can be used in the design of combinational logic, registered logic or finite state machines. Most VHDL language references describe the language constructs and how these behave during simulation. The paper gives some useful tips on how to use the language to best advantage during the hardware design process and describes the implementation of commonly used VHDL constructs