• DocumentCode
    2862023
  • Title

    System-Level Power Management for Low-Power SOC Design

  • Author

    Jing-jing, Zhu ; Feng, Lu

  • Author_Institution
    IoT Eng., Jiangnan Univ., Wuxi, China
  • fYear
    2011
  • fDate
    14-17 Oct. 2011
  • Firstpage
    412
  • Lastpage
    416
  • Abstract
    From the system-level of low power consumption view, this article puts forward in software management proposal. Power management unit are introduced. Especially power states transition scheme has been worked out. And the scheme for device power management is elaborate. We applied the method to a complicated SoC and the experimental results prove that this method could reduce system power very greatly with no performance penalty on the chip.
  • Keywords
    power consumption; software management; system-on-chip; low power SOC design; power consumption; software management; states transition scheme; system level power management; Clocks; Phase locked loops; Phasor measurement units; Power demand; Registers; Switches; System-on-a-chip; Low-power design; System-on-chip; power management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Distributed Computing and Applications to Business, Engineering and Science (DCABES), 2011 Tenth International Symposium on
  • Conference_Location
    Wuxi
  • Print_ISBN
    978-1-4577-0327-0
  • Type

    conf

  • DOI
    10.1109/DCABES.2011.87
  • Filename
    6118697