DocumentCode
2863141
Title
Development of Digital Television Network Tester Based on Dual CPU Architecture
Author
Junhua, Wang ; Hengshan, Geng
Author_Institution
Coll. of Comput. Sci. & Software, Hebei Univ. of Technol., Tianjin, China
fYear
2009
fDate
1-3 Nov. 2009
Firstpage
8
Lastpage
10
Abstract
This article describes a kind of embedded solution for Digital Television Network Tester adopting ARM-DSP dual processor system architecture. This architecture considers flexible control of ARM processor and strong signal-processing capability of DSP processor, combines decoding technology of digital television transmission channel and embedded technology. The advantage of abundant software and nice-looking interface of embedded system software is fully demonstrated. Portable digital television network tester of Dual CPU architecture presents stable performance, low cost, integrating function of memory, analysis and communication, and it can be extensively applied in monitoring and diagnosis for various kinds of digital network.
Keywords
decoding; digital signal processing chips; digital television; embedded systems; signal processing; ARM DSP dual processor system architecture; abundant software; considers flexible control; decoding technology; digital television network tester; digital television transmission channel; dual CPU architecture; embedded solution; embedded system software; memory integrating function; portable digital television network tester; signal processing capability; Computer architecture; Decoding; Digital TV; Digital signal processing; Embedded software; Embedded system; Process control; Signal processing; Software systems; System testing; ARM; DSP; Dual CPU architecture; SIO; VDK operating system;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Networks and Intelligent Systems, 2009. ICINIS '09. Second International Conference on
Conference_Location
Tianjin
Print_ISBN
978-1-4244-5557-7
Electronic_ISBN
978-0-7695-3852-5
Type
conf
DOI
10.1109/ICINIS.2009.11
Filename
5366179
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