DocumentCode
2864467
Title
LSI chip design for testability
Author
Dasgupta, S. ; Eichelberger, E. ; Williams, Tyson
Author_Institution
IBM Corp., Poughkeepsie, NY, USA
Volume
XXI
fYear
1978
fDate
15-17 Feb. 1978
Firstpage
216
Lastpage
217
Abstract
The design of LSI chips for testability using shift register latches as the basic storage units in level sensitive scan application will be discussed. Examples of circuits using this technique will also be offered.
Keywords
Automatic testing; Chip scale packaging; Circuit testing; Clocks; Fault detection; Feedback loop; Large scale integration; Latches; Logic testing; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1978.1155765
Filename
1155765
Link To Document