• DocumentCode
    2864868
  • Title

    Model for a 15ns 16K RAM with Josephson junctions

  • Author

    Broom, R. ; Gueret, P. ; Kotyczka, W. ; Mohr, T. ; Moser, A. ; Oosenbrug, A. ; Wolf, Philip

  • Author_Institution
    IBM Research Laboratory, Zurich, Switzerland
  • Volume
    XXI
  • fYear
    1978
  • fDate
    15-17 Feb. 1978
  • Firstpage
    60
  • Lastpage
    61
  • Abstract
    A RAM cross section, intended as a feasibility model for a 16K bit memory with an access time of approximately 15ns, has been developed. The design, including array, drivers and decoders, will be described and test results offered.
  • Keywords
    Current measurement; Decoding; Delay; Inductance; Inverters; Josephson junctions; Logic arrays; Semiconductor device measurement; Superconducting films; Time measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1978.1155788
  • Filename
    1155788
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2864868