DocumentCode
2865007
Title
Sub-100ps experimental Josephson interferometer logic
Author
Klein, M. ; Herrell, D. ; Davidson, A.
Author_Institution
IBM Research Center, Yorktown Heights, NY, USA
Volume
XXI
fYear
1978
fDate
15-17 Feb. 1978
Firstpage
62
Lastpage
63
Abstract
This paper will cover experimental Josephson interferometer logic gates fabricated in a 5 μm technology with 1 μW/gate dissipation, citing measured delays of 40, 95 and 120ps for OR, AND and master slave latch, respectively.
Keywords
Circuit testing; Delay effects; Feeds; Inverters; Josephson junctions; Latches; Oscilloscopes; Power supplies; Superconducting integrated circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1978.1155795
Filename
1155795
Link To Document