Title :
Sub-100ps experimental Josephson interferometer logic
Author :
Klein, M. ; Herrell, D. ; Davidson, A.
Author_Institution :
IBM Research Center, Yorktown Heights, NY, USA
Abstract :
This paper will cover experimental Josephson interferometer logic gates fabricated in a 5 μm technology with 1 μW/gate dissipation, citing measured delays of 40, 95 and 120ps for OR, AND and master slave latch, respectively.
Keywords :
Circuit testing; Delay effects; Feeds; Inverters; Josephson junctions; Latches; Oscilloscopes; Power supplies; Superconducting integrated circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155795
