DocumentCode :
2865176
Title :
Low voltage superjunction power MOSFET: An application optimized technology
Author :
Rutter, Phil ; Peake, Steven T.
Author_Institution :
NXP Semicond., Manchester, UK
fYear :
2011
fDate :
6-11 March 2011
Firstpage :
491
Lastpage :
497
Abstract :
A detailed analysis of the power loss mechanisms in synchronous DC-DC converters has been undertaken to identify the critical MOSFET parameters that require improving to ensure that system efficiencies and power densities continue to increase. The analysis shows that the commonly used figures of merit (FOMs) based on QG and QGD (i.e. RDS(on)×QG and RDS(on)×QGD) are no longer sufficient when developing power MOSFET technologies, and if followed religiously, can lead to non-optimal technology choices. The insights gained from this work have been employed to define a set of FOMs that were then used to develop a new low voltage power MOSFET technology. The resulting 30V technology, based on the superjunction concept, is ideally suited for DC-DC conversion and in contrast to competing technologies such as lateral and split-gate trench MOSFETs, this approach simultaneously offers low specific RDS(on), QG, QGD, QOSS, and high gate-bounce immunity.
Keywords :
DC-DC power convertors; power MOSFET; application optimized technology; figures of merit; high gate-bounce immunity; lateral MOSFET; low voltage superjunction power MOSFET; split-gate trench MOSFET; synchronous DC-DC converters; voltage 30 V; Computer architecture; FETs; Logic gates; Power MOSFET; Split gate flash memory cells; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE
Conference_Location :
Fort Worth, TX
ISSN :
1048-2334
Print_ISBN :
978-1-4244-8084-5
Type :
conf
DOI :
10.1109/APEC.2011.5744642
Filename :
5744642
Link To Document :
بازگشت