Title :
High speed NMOS circuits for ROM accumulator and multiplier type digital filters
Author :
De Man, H. ; Vandenbulcke, C. ; Chappelen, M.
Author_Institution :
Catholic University of Leuven, Heverlee, Belgium
Abstract :
A two-clock, four-phase NMOS ROM accumulator-shift circuit, operating at a filter bit rate in excess of 10MHz- less than 5mm2for a second-order section - will be reported in this paper. A four-phase pipeline multiplier occupies 0.2mm2/cell and operates at a 20MHz-bit rate.
Keywords :
Capacitors; Clocks; Coupling circuits; Digital filters; Equations; Logic; MOS devices; Read only memory; Scanning probe microscopy; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155815
