Design of IRIG-B code DC output module base on CPLD and AVR MCU

In “BEIDOU” satellite time synchronization system, timing information received by the local timing terminal through wireless satellite channel need to transmit to the user by means of frame encapsulation. IRIG-B code is a kind of serial code and is selected to package the timing frame. The AVR microcontroller, AT90S2313, first stores the timing information received from management module at memory units addressed from 60H to 6DH,and then according to the rules of B-Code, this information are rewrite to the memory units addressed from 70H to 7BH. In the memory units addressed form 80H to 8CH, a data table has been structured to illustrate the position of “P” code element in a frame. The CPLD chip, EPM7064STC44, triggered by the 1PPS signal, will send a serial of interrupt requests to MCU with the frequency of 1 KHz to output the timing frame until a frame has been transmitted. The external SRAM is not used and the system is proved to be stably and efficiently.