Title :
Verification of a 32-bit RISC processor core
Author :
Kasanko, Tuukka ; Nurmi, Jari
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Abstract :
Verification is currently the most time consuming task in the development of new designs. Automation must be introduced in order to achieve satisfactory results within reasonable time. This work presents how verification was conducted for one SoC component, a 32-bit RISC processor core. A wide variety of tools and methods were used in the process.
Keywords :
circuit CAD; integrated circuit design; logic CAD; reduced instruction set computing; system-on-chip; 32 bit; RISC processor core design verification; SoC component; design automation; verification methods; verification time; verification tools; Automatic testing; Automation; Documentation; Microprocessors; Personnel; Real time systems; Reduced instruction set computing; Registers; System testing; Timing;
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
DOI :
10.1109/ISSOC.2004.1411161
