DocumentCode :
2866387
Title :
Topology design for global link optimization in application specific network-on-chips
Author :
Sigüenza-Tortosa, David A. ; Nurmi, Jari
Author_Institution :
Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
fYear :
2004
fDate :
16-18 Nov. 2004
Firstpage :
135
Lastpage :
138
Abstract :
A new algorithm for application-specific network-on-chip design and optimization is presented. The algorithm uses packet-scheduling and traffic modelling concepts to estimate the degree of interaction of several communication channels (congestion) on a given design. It is implemented as part of a network design software package that includes other optimization criteria, like power consumption and reliability.
Keywords :
circuit optimisation; logic design; packet switching; telecommunication congestion control; telecommunication network topology; application specific NoC; communication channel congestion; communication channels interaction degree; global link optimization; network design software package; network-on-chip topology design; packet-scheduling; power consumption optimization; reliability optimization; traffic modelling; Algorithm design and analysis; Application software; Communication channels; Design optimization; Network topology; Network-on-a-chip; Software design; Software packages; Telecommunication traffic; Traffic control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
Type :
conf
DOI :
10.1109/ISSOC.2004.1411167
Filename :
1411167
Link To Document :
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