Title :
Combination of TCAD and physical MOSFET model for LSI development time reduction
Author :
Ishimaru, K. ; Kasai, K. ; Fukaura, Y. ; Okayama, Y. ; Imamura, T. ; Irie, S. ; Hirano, T. ; Watanabe, K. ; Ueno, M. ; Hashimoto, K. ; Matsuoka, F.
Author_Institution :
Memory LSI R&D Center, Toshiba Corp., Yokohama, Japan
Abstract :
Advantage of MOSFET SPICE parameter prediction by combining TCAD and BSIM3 model is presented. This method can release sufficient SPICE parameters without wafer fabrication. Lithography TCAD can reduce pattern optimization work. Device development time reduction is also presented with fabricated SRAM results
Keywords :
MOS memory circuits; SPICE; SRAM chips; integrated circuit modelling; large scale integration; lithography; technology CAD (electronics); BSIM3; LSI development time; MOSFET; SPICE parameter prediction; SRAM; TCAD; lithography; pattern optimization; physical model; Circuit synthesis; Fabrication; Large scale integration; Lithography; MOSFET circuits; Predictive models; Random access memory; SPICE; Semiconductor device modeling; Time to market;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-5921-6
DOI :
10.1109/ASMC.2000.902567
