DocumentCode
2866518
Title
Optimizing Web Browser on Many-Core Architectures
Author
Fan, Lingjun ; Shi, Weisong ; Tang, Shibin ; Yan, Chenggang ; Fan, Dongrui
Author_Institution
Key Lab. of Comput. Syst. & Archit., Inst. of Comput. Technol., Beijing, China
fYear
2011
fDate
20-22 Oct. 2011
Firstpage
173
Lastpage
178
Abstract
As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.
Keywords
hypermedia markup languages; multiprocessing systems; online front-ends; 64-core architecture; Godson-T processor; HTML source data; URL requests; Web browser optimization; data locality; data transfer agent; handheld devices; local buffer; mainstream processor; multi-many-core architecture; off-chip memory access reduction; on-chip scratch-pad memory; Browsers; HTML; Layout; Multicore processing; System-on-a-chip; Web pages; Data Transfer Agent; Godson-T; Many-Core Architecture; Scratchpad Memory; Web Browser;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Computing, Applications and Technologies (PDCAT), 2011 12th International Conference on
Conference_Location
Gwangju
Print_ISBN
978-1-4577-1807-6
Type
conf
DOI
10.1109/PDCAT.2011.61
Filename
6118943
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