High speed and low power on-chip micro network circuit with differential transmission line

Author

Gomi, Shinichiro ; Nakamura, Kohichi ; Ito, Hiroyuki ; Sugita, Hideyuki ; Okada, Kenichi ; Masu, Kazuya

Author_Institution

Precision & Intelligence Lab., Tokyo Inst. of Technol., Yokohama, Japan

fYear

2004

fDate

16-18 Nov. 2004

Firstpage

173

Lastpage

176

Abstract

This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 μm and 0.18 μm CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.

Keywords

CMOS digital integrated circuits; RC circuits; RLC circuits; coplanar transmission lines; driver circuits; high-frequency transmission lines; integrated circuit interconnections; low-power electronics; 0.18 micron; 0.35 micron; 10 Gbit/s; 4 Gbit/s; 8 Gbit/s; CMOS; RC differential transmission line; RLC differential transmission line; high speed micro network circuit; inter-chip communication; intra-chip communication; low power on-chip micro network circuit; pulse signal transmission; receiver circuit; CMOS process; CMOS technology; Circuit simulation; Distributed parameter circuits; Energy consumption; Network-on-a-chip; Power transmission lines; Pulse circuits; RLC circuits; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2004. Proceedings. 2004 International Symposium on

Print_ISBN

0-7803-8558-6

Type

conf

DOI

10.1109/ISSOC.2004.1411178

Filename

1411178