Design for verification of a PCI bus in SystemC

In this paper, we present an approach to design and verify SystemC intellectual properties (IPs). We considered as an illustrative case a PCI bus modeled as a monitor module that can be interfaced to existent SystemC IPs. We defined three design steps where we first model the bus in UML; then, design it completely with abstract state machines (ASM); and, finally, translate the ASM code to SystemC. We considered an intermediate ASM representation in order to extract the finite state machine of the bus that can be used for model checking of PSL properties. The final SystemC monitor block can be seen as a stand-alone PCI IP as well as a verification module to validate other SystemC PCI compatible devices. Besides, our design offers a flexible and easy to configure an IP that supports a large number of master/slave devices.