Title :
3D graphics circuits for 3G multimedia terminals
Abstract :
Summary form only given. The development of system-on-chip technology drives various multimedia and even 3D graphics capabilities into 3G multimedia terminals. The 3D applications are attractive to the mobile market, however, implementing them requires a huge amount of parallel calculations and memory bandwidth within the boundary of limited battery power. In this talk, we discuss ´how to´ and ´where to´ apply various circuits and architecture techniques to the 3D graphics pipeline to achieve low power consumption, with the example of RAMP (RAM processor) by KAIST research group and several other world-class mobile 3D engines.
Keywords :
3G mobile communication; computer graphics; low-power electronics; multimedia communication; multimedia computing; parallel processing; system-on-chip; 3D graphics circuits; 3D graphics pipeline; 3G multimedia terminals; RAM processor; RAMP; battery power limitations; low power consumption; mobile 3D engines; parallel calculations; system-on-chip technology; Bandwidth; Batteries; Circuits; Energy consumption; Graphics; Multimedia systems; Pipelines; Random access memory; Read-write memory; System-on-a-chip;
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
DOI :
10.1109/ISSOC.2004.1411186
