• DocumentCode
    2866844
  • Title

    Wafer probe process verification tools

  • Author

    Rodriguez, Eduardo ; Cano, Cristina ; Sanchez-Vicente, J. ; Moreno, Julián

  • Author_Institution
    Lucent Technol. ME, Madrid, Spain
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    207
  • Lastpage
    212
  • Abstract
    We present some tools we have developed that ensure the good quality of the wafer probing, or wafer test, process. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield from being affected. The most common patterns of failures are: A certain category failing consecutively, a certain test failing above statistical limits expected, based on the historical results of that product, same wafers yielding different in two different testers, and results in a lot going worse wafer by wafer. For addressing these issues, we have generated a set of programs that are run at the end of every wafer tested, in real time, and that generate alarms and tell actions to the operator when the above problems are detected
  • Keywords
    electronic engineering computing; inspection; integrated circuit testing; integrated circuit yield; quality control; software tools; statistical process control; alarms; consecutive failures; failure patterns; operator interface; process quality; process verification tools; split limits; statistical bin limits; test repeatability; three-sigma limits; wafer probing; wafer test; yield loss; Aluminum; Clamps; Instruments; Needles; Pins; Probes; Relays; Semiconductor device manufacture; Semiconductor device testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI
  • Conference_Location
    Boston, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-5921-6
  • Type

    conf

  • DOI
    10.1109/ASMC.2000.902589
  • Filename
    902589